DFT Technical Publications
Layout-Aware Diagnosis
Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes of high-quality diagnosis results to determine yield limiters. To be of value for both engineers, a diagnosis tool needs to be accurate, with high resolution and, meaningful defect classifications.
Significant improvements have been made in scan logic diagnosis algorithms. However, the defect classifications, accuracy, and resolution provided by diagnosis tools are, in general, insufficient for effective yield and failure analysis. Through layout information YieldAssist improves all three items, becoming a powerful tool in the hands of the failure analysis and yield engineer.
Layout information enables YieldAssist to improve accuracy and resolution by 70% to 85% depending on the defect type and allows layout-validated defect types. More meaningful reporting for example on the polygon level prepares the diagnosis results for direct use by engineers. In the appendix, we discuss layout-aware flows and file formats, and summarize YieldAssist’s true layout-aware approach.
Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Reduced pin count testing (RPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying RPCT, devices can be easily tested on structural DFT testers at a cost of about $200/pin compared to the high-end functional testers that cost almost $8,000-10,000/pin.
By combining RPCT with test compression, we have extended the capabilities of multi-site testing to allow application of at-speed test patterns using low-cost testers that are seriously pin-limited. We were able to free up device I/O by 90%. The method proposed here enables gains in test coverage with less application time and minimal effects on design and test overhead. It can be used in multi-site test, with simpler fixturing.
High Quality Test Solutions for Secure Applications
The Next Generation of Embedded Test Compression: TestKompress(r) Xpress Compactor
YieldAssist and Its Successful Industrial Applications
Yield Improvement, Verified Flow, Accuracy, Layout Aware and Volume Diagnosis
Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. The process and design variances require checks for the design-for-manufacturing (DFM) issues in order to achieve a high yield. Scan diagnostics targeted for the nanometer designs can provide quick, accurate and reliable failure information from the production environment. The sorted, fault classified and physically linked scan diagnosis results can, in turn, provide the guides for DFM checks. High volume diagnosis provides data to yield management system for statistical analysis. YieldAssist, Mentor's scan diagnosis solution has been adopted by many customers to meet these goals. This paper explains the technology behind it, discusses its applications and shows the results.
TestKompress 2007
The Robustness of Various Test Compression Techniques
Improving Yield - Bridging Fault ATPG in FastScan and TestKompress with Net Pair Identification using Calibre
Beyond Pass/Fail Testing: Using Failure Data from Manufacturing Test for Yield
At-Speed and Advanced Fault Models for Achieving High Quality Test
Design Flows Using TestKompress
Different embedded compression products and technologies have been tried and discarded as the marketplace selects the solution that best meets all the requirements. Users have determined that a successful embedded compression tool is required to:
- Maintain high test quality (i.e. support all fault types)
- Achieve high test compression of both test time and test data (up to 100X)
- Have little or no impact on the functional design
- Add minimal area
- Easily fit into the design flow
As evidenced by its widespread industry adoption, TestKompress has met or exceeded all of these requirements while requiring as few as a single scan channel and offering diagnostics directly from compressed patterns. While Design-For-Test (DFT) groups are typically most concerned with high test quality and Operations Test is focused on reducing test time and data, design teams are most concerned with how any tool or methodology will impact the design and how it will fit into their existing design flow. This paper will describe the various design flows that TestKompress supports for the generation, insertion and synthesis of its embedded compression logic. The advantages of each flow are discussed so that the designer can decide which best fits into his or her existing design flow.