IC Nanometer Design
- Efficient handoff between IC design and manufacturing
- Provides necessary tie between physical verification and DFT
- Single, streamlined design flow for AMS SoC design
Technical Events:
- Calibre Design-to-Silicon Platform Workshop
Jan 13, 2009 - San Jose, CA
- Accelerating Custom IC Implementation: Speed without compromise
- online
- Advanced DFM and AAA — Mentor and TSMC Collaborate for Success
- online
- Approaching Yield in the Nanometer Age
- online
Featured IC Nanometer Design Techpubs
Applying Assertion-Based Formal Verification to Verification Hot Spots
Based on our experience helping many design teams deploy assertions and formal verification, we recommend deploying ABV (including formal model checking) on the most salient verification hot spots in a design, following a seven-step, formal verification planning process. By focusing ABV on verification hot spots, a design team can adopt ABV incrementally as they continue to use their simulation-based methodology. This has the added benefit of minimizing the risks involved with adopting a new methodology while maximizing the return-on-investment.
Post-Layout Analysis with Eldo and Eldo RF
It is important to verify the behavior and interaction of digital, analog and RF circuitry together in the presence of layout parasitics. This also means being able to debug the design in the presence of parasitics, and mastering large amounts of parasitic data. An approach is presented which allows the design engineer to use Eldo® and Eldo RF to achieve the best combination for accuracy, performance and debugging.
Phase-Locked Loop Simulation with Modulated Stead-State Analysis
Currently, a Phase-Locked Loop remains one of the more difficult designs to characterize; the transient simulation used is a large time consumer. The time step used for the simulation is given by the Radio Frequency (RF) signal provided by the VCO that could be 1000 times greater than the low frequency signal (i.e. reference clock).
News and Related Articles
- Mentor Graphics Olympus-SoC Place-and-Route System Qualifies for TSMC 40nm ProcessesDec 11, 2008
- NEC Electronics Selects Mentor Graphics Calibre nmLVS for Advanced Circuit Characterization at 40nm and BelowNov 13, 2008
- Mentor Graphics Boosts Eldo Simulator Performance with Generalized Multi-threading TechnologyNov 4, 2008
