Techniques for Routing High-Speed Designs Seminar
There are currently no dates scheduled for this event
Overview
Increasing bus speeds, faster switching speeds, and clock speeds that continue to increase at 40% a year are all causes of high-speed design problems and, hence, cause of concern to you, the PCB designer. PCB Designers need to ensure that their designs don't introduce delays or unintentionally create antennas that could lead to timing problems or logic failures. By carefully managing layer definition, trace coupling, and route widths and lengths, you can avoid these problems. Attend this FREE seminar to learn techniques for gaining superior control over high-density boards and length-constrained nets.
TIME: 10:00 am - 1:00 PM PST
Who Should Attend
- PCB designers, regardless of which tool you use
- Customers who use PADS Layout, rather than PADS Router, to route their boards
What You Will Learn
- How to avoid having traces behave like transmission lines
- The controls required for high-speed design
- Advanced constraint definition
- High-speed rule definition
- Tips for autorouting with high-speed rules
- Batch verification of high-speed rules
- Using BGA fanouts to route high-density designs
- How to set vias at SMD
- How to route with blind & buried vias